NST 2007 Extended Summary

This investigation proposes the novel radix4 and radix-4 algorithms with the low computational complexities of the radix-16 and radix-64 algorithms but the lower hardware requirement of the radix-4 algorithm. Base on the serial delay feedback path pipeline architecture, the proposed design adopts a multiplierless radix-4 butterfly structure to support 4096-point FFT/IFFT computations. Moreover, the retrenched constant multiplier and eight-folded complex multiplier structures are adopted to decrease the multiplier cost and the coefficient ROM size with the complex conjugate symmetry rule and subexpression elimination technology. The comprehensive comparison results reveal that the proposed R4SDF design achieves the highest cost efficiency.